Advanced CMOS technology employs complementary n- and p-wells in order to simultaneously optimize the NMOS and PMOS transistors. The conventional complementary well formation process employs one or two microlithography masking steps. The two mask fabrication process has the advantage that it does not degrade the silicon surface planarity or topography. This is an important requirement in advanced CMOS technology where even a small (e.g. a few thousand angstroms) step between the n-well and p-well regions can result in gate wavelength variations between the NMOS and PMOS transistors. The CMOS transistor gate length variations can degrade manufacturability and yield. As a result, the process simplicity of the conventional one mask fabrication process is not a strong and sufficient advantage/improvement to justify its use in the semiconductor technology since the one mask process creates a step or undesired surface topography during the process.
The surface topography problem in the conventional one mask fabrication process is generated by a selective thermal oxidation process. An example of a one mask fabrication process is disclosed in U.S. Pat. No. 5,252,501 (the "'501 patent"). In the '501 patent, the process begins with an oxide/nitride stack patterned and used (usually along with the photoresist mask) as an ion implantation mask to define one of the wells. After removal of the photoresist, an oxidation step is performed which selectively defines an oxide hard mask over the implanted area. A second ion implantation step is used to define the second (opposite) well regions. As recognized in the '501 patent, this process generates an undesired surface topography or step between the n- and p-well regions due to the silicon consumption by the selective thermal oxidation step.
The '501 patent attempts to solve this step problem by using selective semiconductor growth processes. This solution to the step problem, however, does not solve the problem if conventional materials and conventional processes are used.